Demodulator using cordic rotator-based digital phase locked loop for carrier frequency correction

ABSTRACT

A digital data demodulator employs a cordic rotator-based, digital phase locked loop for carrier frequency tracking. Digitized I and Q channels downconverted to baseband using a fixed frequency oscillator are coupled to a digital cordic rotator. The cordic rotator iteratively executes pipelined phase-rotational adjustments of its digitized in-phase and quadrature inputs, in association with a pipelined reduction of the accumulated value of a phase angle vector code generated by digital phase error detection logic circuitry to which rotated I and Q outputs of the cordic rotator are applied. The phase error representative code vector is coupled through a digital loop filter as a reference angle input to the cordic rotator. The cordic rotator iteratively rotates the I and Q channel values that reduce the accumulated phase error to zero.

FIELD OF THE INVENTION

[0001] The present invention relates in general to communicationsystems, and is particularly directed to a digital data demodulatorarchitecture, that employs a cordic rotator-based, digital phase lockedloop for carrier frequency acquisition and tracking.

BACKGROUND OF THE INVENTION

[0002] The radio frequency (RF) and intermediate frequency (IF) stagesof conventional radio subsystems (including those which employ digitalsignal processing components), such as but not limited to modulator anddemodulator stages, typically employ both fixed frequency and voltagecontrolled crystal oscillators as part of their frequency conversionstages (mixers) and phase locked loop circuits. A conventional phaselocked loop for a demodulation stage of a conventional “digital” radiofor demodulating a spread spectrum-modulated BPSK signal, as anon-limiting example, is diagrammatically illustrated in FIG. 1 ashaving an input port 10, to which an incoming signal to be demodulatedis applied. Input port 10 is coupled to respective in-phase (I) andquadrature phase (Q) channel mixers 11 and 13, which multiply theincoming signal by relative phase quadrature reference frequency signalsgenerated by a voltage controlled local oscillator (VCO) 15 and anassociated 90° phase shifter 17, so as to produce down-converted(baseband) I and Q channel signals.

[0003] The down-converted (baseband) I and Q channel signals output bymixers 11, 13 are digitized by an analog-to-digital converter 21 andthen despread by a correlator 23. The respective despread baseband I′and Q′ channels output by the correlator 23 are coupled over respectivemultibit links 31 and 32 to digitally implemented phase error detectionlogic circuitry 33, which outputs a digital vector (code) representativeof the (carrier frequency offset associated) phase error in thedownconverted signals. This phase error code is coupled through adigital loop filter 35 to a digital-to-analog converter (DAC) 37, whichconverts the phase error code into an analog voltage for adjusting theoutput frequency of the VCO 15.

[0004] Because oscillator circuits of the type used in the carriertracking stage of FIG. 1 employ analog components (VCO 15), they sufferfrom a number of deficiencies. For example, their output frequencieswill vary with environmental conditions, such as time (aging) andtemperature, as well as with other less influential factors. Inaddition, component-to-component manufacturing tolerances of these partsare satisfactory only within a prescribed range—usually specified in thehundreds of parts per million (ppm). Further, compared to othercomponents in the radio, oscillators are relatively expensive and proneto mechanical failure.

[0005] Due to the inherent inaccuracies in oscillator components of aradio receiver prevent data from being perfectly demodulated anddelivered to downstream baseband processing circuitry with precisereplication, compensation circuitry must be incorporated into theradio's timing recovery and data demodulation signal processing stages.These circuits traditionally utilize additional voltage controlledoscillator components, which are tuned to frequencies such that theinaccuracies of the crystal and voltage controlled oscillator componentsused in each of the transmitter and receiver portions of the radio canbe effectively eliminated on a long term averaged basis. Unfortunately,employing a voltage controlled oscillator in the compensation circuitintroduces yet another level of inaccuracy, and adds to the cost of theoverall radio design.

SUMMARY OF THE INVENTION

[0006] In accordance with the present invention, the above describedshortcomings of conventional analog voltage controlled oscillator-basedradio systems are effectively obviated by a new and improveddigital-based data demodulator architecture, that employs a cordicrotator-based digital phase locked loop for carrier frequency tracking,and thereby removes the voltage controlled oscillator and its associatedproblems from the phase locked loop. In a demodulator application, areceived signal, such as a spread spectrum-modulated BPSK signal, ismultiplied in respective in-phase (I) and quadrature phase (Q) channelmixers by relative phase quadrature reference frequency signals producedby a fixed frequency (e.g., crystal) oscillator and an associated 90°phase shifter to produce down-converted (baseband) I and Q channels.

[0007] The I and Q channels are digitized and then despread by acorrelator. The respective despread baseband I and Q channels arecoupled to respective inputs of a digital cordic rotator, which executesiterative phase-rotational adjustments of its digitized in-phase andquadrature inputs, in accordance with a phase angle vector codegenerated by digital phase error detection logic circuitry to which therotated I and Q outputs of the cordic rotator are applied. The phaseerror representative code vector is coupled through a digital loopfilter as a reference angle input to the cordic rotator. The cordicrotator iteratively rotates the I and Q channel values over a prescribednumber of processing cycles.

[0008] Pursuant to a preferred embodiment, the cordic rotator includes aquadrant adjustment section upstream of respective I and Q channelrotation iteration loops, and a phase angle quadrant adjustment sectionupstream of a phase angle iteration loop. Each iteration through thepipeline signal processing paths for the respective I channel and Qchannel rotation iteration loops and a phase angle iteration loopcomprises four quarter cycles. The quadrant adjustment section is usedat initialization to perform a quadrant adjustment of the I and Q inputvalues, based upon the sign of the angle of rotation e supplied from thedigital loop filter. In association with initialization of the I and Qchannels, a phase angle quadrant adjustment section performs an offsetcorrection of the vector code value of the angle of rotation θ, inaccordance with whether the phase angle code vector falls within aprescribed window.

[0009] During the first subportion (quarter cycle) of a respectiveiteration, quadrant-adjusted IP and QP values are latched intoassociated I and Q registers, an incremental angle control codeassociated with the arctan of an iteration-defined power of one-half isgenerated, and the current value of iterated phase angle value islatched in an updated phase angle or β register. During a second quartercycle, the respective values of the I and Q vectors are divided by two,by associated right-shift logic circuits and the results are multipliedby the most significant bit of the phase angle code β to produce delta Iand Q codes. Also a delta phase angle value based upon the incrementalangle code is stored.

[0010] During the third quarter cycle, an updated phase angle valuecorresponding to the sum of the delta phase angle value and the updatedphase angle β is generated and latched. Also the delta I and Q codesproduced during the second quarter cycle are summed with the previous Iand Q values to produce updated I and Q codes, respectively. In thefourth cycle, the updated I and Q codes are latched, thus completing oneiteration.

[0011] This process is repeated for K iterations (with the exception ofthe initialization operations carried out by the quadrant adjustmentsection for the I and Q loops and the phase angle quadrant adjustmentsection for the phase angle loop). In the fourth quarter cycle of theKth iteration, the adjusted values of the I and Q channel codes arelatched into output registers to provide respective ‘cordic-rotated’ Iand Q channel output values.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 diagrammatically illustrates a phase locked loop for ademodulation stage of a conventional digital radio;

[0013]FIG. 2 diagrammatically illustrates the overall architecture of ademodulator employing a cordic rotator-based digital phase locked loopin accordance with an embodiment of the invention; and

[0014]FIG. 3 diagrammatically illustrates an embodiment of the digitallogic architecture of a cordic rotator that may be employed in the phaselocked loop of FIG. 2.

DETAILED DESCRIPTION

[0015] Before describing in detail the new and improved cordicrotator-based digital phase locked loop of the present invention, itshould be observed that the invention resides primarily in what iseffectively a modular arrangement of conventional communicationsignaling hardware and signal processing components and attendantsupervisory communications microprocessor circuitry and applicationsoftware therefor, that controls the operations of such components. In apractical implementation that facilitates their incorporation intowireless telecommunication equipment, such as but not limited to aspread spectrum microwave (T1) radio, these modular arrangements may beimplemented as field programmable gate array (FPGA) and/or applicationspecific integrated circuits (ASICs). In terms of a practical hardwareimplementation, to be described, digital ASICs are preferred.

[0016] Consequently, the configuration of such circuits and componentsand the manner in which they are interfaced with associated radiocommunication subsystems have, for the most part, been illustrated inthe drawings by readily understandable block diagrams, which show onlythose specific details that are pertinent to the present invention, soas not to obscure the disclosure with details which will be readilyapparent to those skilled in the art having the benefit of thedescription herein. Thus, the block diagram illustrations of the Figuresare primarily intended to show the major components of a demodulatoremploying the cordic rotator-based phase locked loop in a convenientfunctional grouping, whereby the present invention may be more readilyunderstood.

[0017] The overall architecture of a demodulator employing a cordicrotator-based digital phase locked loop in accordance with anon-limiting, but preferred, embodiment of the invention isdiagrammatically illustrated in FIG. 2 as comprising an input port 41,to which an incoming signal, such as a spread spectrum-modulated BPSKsignal used to transport T1 digital communication channels is applied.As in the conventional architecture of FIG. 1, the input port 41 iscoupled to respective in-phase (I) and quadrature phase (Q) channelmixers 42 and 43, which multiply the incoming signal by relative phasequadrature reference frequency signals generated by a local oscillator(VCO) 45 and an associated 90° phase shifter 47, to produce a pair ofdown-converted (baseband) I and Q channel signals. Unlike thearchitecture of FIG. 1, however, local oscillator 45, rather than beinga voltage controlled oscillator, is a fixed frequency device, such as arelatively inexpensive crystal oscillator, that readily lends itself touse in a consumer oriented product.

[0018] The down-converted (baseband) I and Q channel signals output byrespective mixers 42 and 43 are digitized by an analog-to-digitalconverter 51 and then despread by a correlator 53. The respectivebaseband digital I and Q channels as despread by the correlator 53 arecoupled to respective IP and QP inputs of a cordic rotator 60 (shown indetail in FIG. 3 to be described). As pointed out briefly above, thecordic rotator 60 is operative to execute iterative frequencyadjustments of its digitized in-phase and quadrature inputs IP and QP,in accordance with a phase angle vector code generated by digital phaseerror detection logic circuitry 61, as representative of the carrierfrequency offset associated phase error in the phase-corrected digitalcodes I′ and Q′. This phase error representative code vector is coupledthrough a digital loop filter 63 as a reference angle input 65 to thecordic rotator 60, which adjusts the phase-corrected codes I′ and Q′over a prescribed number of processing cycles, so as to incrementallyrefine the resolution to which the Cartesian components IP an QP arecorrected.

[0019] Referring now to FIG. 3, a non-limiting, but preferred embodimentof the digital logic architecture of a cordic-rotator that may beemployed in the phase locked loop of FIG. 2 is diagrammaticallyillustrated as comprising input ports 71 and 81, which are coupled toreceive the (Cartesian) IP and QP code vectors output by the despreadingcorrelator 53 for the respective I and Q channels. The I channel's inputport 71 is coupled to a first input of a quadrant adjustment (qa)′multiplier 70 of a quadrant adjustment section 75 upstream of respectiveI channel and Q channel rotation iteration loops 100 and 150. The qamultiplier 70 has a second input coupled to the output of a qa valuemultiplexer 90. Similarly, the Q channels input port 81 is coupled to afirst input of a qa multiplier 80, which has a second input coupled tothe output of the qa multiplexer 90.

[0020] The qa multiplexer 90, in association with qa multipliers 70 and80, is used at initialization to perform a quadrant adjustment of the IPand QP values (based upon the sign of the angle of rotation 8 suppliedto the reference angle input 65 from the digital loop filter 63). Thisquadrant adjustment is effected by selectively supplying one of a pairof prescribed digital code values (e.g., +1, −1) to each of the qamultipliers 70 and 80, in accordance with the logical state of aquadrature adjustment carry input (qaci) to its select input from a qaciregister 218 of a phase angle logic circuit 200, to be described. Thequadrant adjustment section 75 further includes an IPqa register 92,into which the output of quadrant adjusted IP value produced bymultiplier 70 is clocked during initialization mode (by a clock signalsourced from a state machine running in the loop's supervisorymicrocontroller, not shown). Similarly, for the Q channel path a QPqaregister 132 stores the output of the Q channel multiplier 80.

[0021] The quadrant-adjusted IP value stored in the IPqa register 92 iscoupled as a first input 93 of an iteration input multiplexer 95 at theupstream end of IP rotation iteration loop 100. Similarly, the quadrantadjusted QP value stored in the QPqa register 132 are coupled as a firstinput 133 of a multiplexer 135, at the upstream end of QP rotationiteration loop 150. As will be described, each I and Q rotationiteration loop is operative to iteratively adjust values of the IP andQP Cartesian vectors to accumulated values that reduce the value of thephase angle e to zero.

[0022] For purposes of providing a non-limiting example, the code widthsof the IP, QP and 6 values may be sixteen bits, and ten iterations maybe employed. Also, in the pipeline signal processing paths through therespective I channel and Q channel rotation iteration loops as well as aphase angle iteration loop, each pipeline stage may comprise fourquarter cycles 0, 1, 2, 3, so that for ten iterations a total of fortyquarter cycles are executed. It should be observed, however, that thecordic rotator architecture and signal processing flow described hereinare not limited to these are any other set of parameters. In theembodiment of FIG. 3, the particular quarter cycle associated with theclocking of a respective component within each rotation iteration loopis denoted in the lower right hand corner of the component. Thus, forexample, the clocking of an I register 101 in loop 100 is shown asassociated with the first quarter cycle (0).

[0023] Within I channel loop 100, iteration input multiplexer 95 has asecond input 94 derived from a downstream I-next (In) register 116. Thatone of the two inputs 93 and 94 to iteration input multiplexer 95 whichis coupled to its output 96 is defined in accordance with the state ofan initial pipeline stage p(0) select line 98 from the state machinerunning in the cordic rotator's supervisory microcontroller. At thebeginning of each iteration sequence, the initial pipeline stage p (0)select line 98 has a first logic value that couples input 93 to themultiplexer output, and thereby couples the quadrant-adjusted IP valuestored in the IPqa register 92 to the output of the multiplexer 95. Forthe remaining iterations of a given sequence, the initial pipeline stagep (0) select line 98 has a second logic value that couples multiplexerinput 94 to its output, and thereby couples the updated IP value storedin register 116 to the output of multiplexer 95.

[0024] The output 96 of the iteration input multiplexer 95 is bufferedin an I register 101 and applied to a differential or ‘delta I’right-shift (divide-by-two) logic circuit 102, and to a first input 111of an adder 110. During the second quarter cycle (1) of each iterationthrough the pipelined rotational adjustment of the IP value, theright-shift logic circuit 102 performs a divide-by-two operation on thecurrent value of the I vector stored in the I register 101.

[0025] The output of the divide-by-two logic circuit 102 is coupled to afirst input of a sign multiplier 104, a second input of which is coupledto receive the sign or most significant bit (e.g. bit 15) of the currentvalue of a (sixteen bit) phase angle (θ) code supplied from phase anglelogic circuit 200. During the third quarter cycle (2) of each iteration,the resulting value is clocked into a delta I register 112, the storedcontent of which is coupled to a first input 121 of an adder 120 in theQ channel path. Adder 110 has a second input 112 coupled to a delta Qregister 152 in the Q channel loop, and a third input 113 coupled toreceive the complement of the most significant bit value β(15) of thephase angle code stored in an update phase angle or ‘β’ register 245 inthe phase angle logic circuit 200, as will be described.

[0026] During the fourth quarter cycle (3) of each iteration, the outputof the I channel adder 110 is clocked into and buffered in (In) register116, the output of which is coupled to the second input 94 ofmultiplexer 95, as described above, and to an IR output register 118.The adjusted value of the I channel code stored in register 116 is notclocked into the IR output register 118 until the fourth quarter cycleof the last or tenth iteration (shown as quarter cycle (40)).

[0027] For the Q channel loop 150, the bit contents of the QPqa register132 are coupled as a first input 133 of Q multiplexer 135, having asecond input 134 coupled to downstream (Qn) register 156. One of the twoinputs 133 and 134 to multiplexer 135 is coupled to its output 136 inaccordance with the state of the p (0) pipeline stage select line 98from the state machine, as described above for the I channel path.During the first quarter cycle (0) of a respective iteration, the output136 of the multiplexer 135 is buffered in a register 141. During asecond quarter cycle (1) of a respective iteration the contents ofregister 141 are coupled into a delta right-shift (divide-by-two) logiccircuit 142, and to a second input 122 of adder 120 in the I channelpath. The divide-by-two logic circuit 142 is coupled to a first input ofa multiplier 144, a second input of which is coupled to receive thecomplement of the most significant bit (e.g. bit 15) of the (sixteenbit) phase angle code supplied from phase angle logic circuit 200. Atthe third quarter cycle (2) of each iteration, the output of multiplier144 is clocked into a delta Q register 152! the stored contents of whichare coupled to the second input 112 of adder 110 in the I channel path,as described above. Adder 120 has a third input 123 coupled to receivethe most significant bit value β(15) of the phase angle code stored in aβ register 245 in the phase angle logic circuit 200. At the fourthquarter cycle (3) of each iteration, the output of the Q channel adder120 is clocked into and buffered in a Q-next (Qn) register 156, theoutput of which is coupled to the second input 134 of multiplexer 135,as described above, and to a QR output register 158. The updated valueof the Q channel code stored in Qn register 156 is clocked into the QRoutput register 158 at the fourth quarter cycle of the last or tenthiteration (shown as quarter cycle (40)) of the updating sequence.

[0028] The phase angle logic circuit 200 is shown as including a phaseangle quadrant adjustment section 201 to which the (sixteen bit) phaseerror representative code vector θ on line 65 from the digital loopfilter 63 is supplied, as described above. The phase angle quadrantadjustment section 201 is employed at initialization to perform apreliminary offset correction of the vector code value of the angle ofrotation θ, as necessary, to conform with the parametric range ofoperation of the cordic rotator.

[0029] For this purpose, the two most significant bits (e.g., bits θ(14)and θ(15) in the present example) are used to provide steering controlfor a three input ‘initialization angle correction’ multiplexer 210. Thetwo most significant bits of the phase angle input code on line 65 arealso coupled to an exclusive-OR circuit 216, the output of which isstored in a qaci register 218. The bit stored in qaci register 218serves as the steering control input to qa multiplexer 90, as describedabove.

[0030] The initialization angle correction multiplexer 210 has a firstinput 211 coupled to receive a first reference angle of ±180°, a secondinput 212 coupled to receive a second reference angle of −180°, and athird input 213 coupled to receive a third reference angle of 0°. One ofthe three inputs to multiplexer 210 is coupled to its output inaccordance with whether the phase angle code vector θ falls within aprescribed window or range (e.g., ±π/2 as determined by the logic valuesof bits θ(14) and θ(15)).

[0031] If the phase angle code vector θ is greater than +π/2,multiplexer 210 steers the value of −π to its output. If the phase anglecode vector θ is less than −π/2, multiplexer 210 steers the value of +πto its output. Otherwise, multiplexer 210 steers the value of 0 to itsoutput. The output of multiplexer 210 is clocked into a qa register 220,the contents of which are applied as a first input 231 of an adder 230,a second input 232 of which is coupled to the phase angle error codeline 65. The output 233 of adder 230, which is an initially ‘corrected’phase angle value, is clocked into a θqa register 235, the bit contentsof which are coupled to a first input 241 of a front end multiplexer 240of phase angle iteration loop 202. Multiplexer 240 has a second input242 coupled to a downstream β-next (βn) register 256.

[0032] A selected one of the two inputs 241 and 242 to the phase angleiteration loop's front end multiplexer 240 is coupled to its output 243in accordance with the state of the p (0) pipeline stage select line 98from the state machine. During the first quarter cycle (0) of arespective iteration, the output 243 of multiplexer 240 is buffered in aβ register 245 and applied to a first input 251 of an adder 250. Asecond input 252 of adder 250 is coupled to a (delta β) register 258,which stores the product produced by a multiplier 260 during a secondquarter cycle (1) of a respective iteration. During a third quartercycle (2) of a respective iteration, the output of adder 250 is bufferedin βn register 256. The contents of βn register 256 are coupled to thesecond input 242 of multiplexer 240, as described above.

[0033] Multiplier 260 has a first input 261 coupled to receive anincremental angle control code supplied by an incremental angle controlcode generator 265. Generator 265 may comprise gate array logiccircuitry or a state machine that is operative to output successivearctan values of powers of ½, in association with the iterative rightshift (divide-by-two) operations carried out by divide-by-two logiccircuit 102 during successive cycles of iterative rotation of thequadrant adjusted I and Q values processed by the loop 100. A secondinput 262 of multiplier 260 is coupled to receive a dbci bit from acontrol logic circuit 270.

[0034] Control Logic circuit 270 has a first input 271 coupled toreceive a first pipeline stage bit p (1), which is coupled through aninverter 280 to a first input of an AND gate 281 and to a first input ofan AND gate 282, the output of which is coupled to a first input of aNOR circuit 283. Control logic circuit 270 has a second input 272coupled to receive the most significant bit value β(15) of the (sixteenbit) phase angle code stored in β register 245. A second input of ANDgate 282 is coupled to receive the most significant bit θ(15) of the (16bit) phase angle code 8 on line 65. The output of AND gate 281 iscoupled as a second input to NOR circuit 283.

[0035] The Boolean operation of logic circuit 270 is such that the NORcircuit 283 supplies the most significant bit value θ(15) as the dbcivalue to the second input 262 of multiplier 260 only at initialization.Thereafter, during successive iterations of the cordic rotator, the dbcivalue to multiplier 260 from NOR circuit 283 is most significant bitvalue β(15) of the current value of β stored in β register 245, so thatthe incremental modification of the currently accumulated value of thephase angle stored in βn register 256 will track each iterativedivide-by-two operation performed in the I and Q channels of loop 100.

[0036] In operation, at initialization for a new set of I channel and Qchannel code vectors output by the despreading correlator 53 to inputports 71 and 81, the IP and QP input values are multiplied in quadrantadjustment multipliers 70 and 80 by one of the two quadrant adjustmentvalues (+1, −1) supplied to multiplexer 90, and the resulting productsare stored in the respective IPqa and QPqa registers 92 and 132. Asnoted above, the quadrant adjustment values are selected by the state ofthe quadrature adjustment carry input (qaci) bit supplied from qaciregister 218 of the phase angle logic circuit 200, in accordance withthe two most significant bits of the phase angle input code on line 65and applied to exclusive-OR circuit 216.

[0037] In association with initialization of the I and Q channels, thephase angle quadrant adjustment section performs the above-describedoffset correction of the vector code value of the angle of rotation e,based upon the two most significant bits of that phase angle vectorcode. The resulting offset phase angle code value is obtained by summing(in adder 230) the offset value latched into qa register 220 frommultiplexer 210, during the first quarter cycle (0) of a first iteration(J=0), with the original phase angle code vector value θ. During thesame (first quarter) cycle, within the I and Q channels, thequadrant-adjusted IP and QP values stored in the respective IPqa andQPqa registers 92 and 132 are coupled through their associatedmultiplexers. 95 and 135 and latched into I and Q registers 101, 141.

[0038] During the second quarter cycle (1), within the phase angle logiccircuit 200, the initially ‘corrected’ phase angle value at the outputof adder 230 is clocked into θqa register 235, and applied throughmultiplexer 240 β to register 245. In addition, the product output ofmultiplier 260 resulting from multiplying the arctan of the currentiteration (J) of the value of ½² by the dbci bit value is latched intothe register 258. Within the I and Q loops, the respective values of theI and Q vectors are divided by two by the right-shift logic circuits102, 142, and the results are multiplied in multipliers 104, 144 by themost significant bit of the phase angle code β stored in the register245 of the phase angle logic circuit 200.

[0039] During the third quarter cycle (2), within the phase angle logiccircuit 200, the summation value output by adder 250 (representative ofan updated or ‘next’ value of β) is latched into βn register 256. Withinthe I and Q channel loops, the outputs of multipliers 104, 144 arelatched into respective registers 112, 142, for application to adders140, 110. In the fourth quarter cycle (3), the outputs of the I and Qchannel adders 110, 140 respectively are clocked into In and Qnregisters 116, 146.

[0040] Except for the initialization operations carried out by thequadrant adjustment section 75 for the I and Q loops and the phase anglequadrant adjustment section 201 for the phase angle loop 200, theabove-operations are repeated for the second (J=1) through Kth (K=9 inthe present example of a ten iteration sequence) iteration. In thefourth quarter cycle of the tenth iteration (shown as quarter cycle(40)), the adjusted values of the I and Q channel codes stored inrespective registers 116 and 146 are into their associated outputregisters 118, 148 to provide respective ‘cordic-rotated’ IR and QRoutput values.

[0041] As will be appreciated from the foregoing description, theshortcomings of conventional analog voltage controlled oscillator-basedradio systems are effectively obviated by the cordic rotator-baseddigital phase locked loop of the present invention, which eliminates theneed for a voltage controlled oscillator and its attendant problems.Advantageously, the digital cordic rotator architecture employsessentially add and subtraction operations, and performs divisions by ashift operation, thereby simplifying its digital implementation. Thisnot only reduces the sources of noise (including leakage), but reducesthe number of components to the extent that the cost of the digitallogic for the cordic rotator is considerably less than that associatedwith conventional components (multipliers and voltage controlledoscillators).

[0042] While we have shown and described an embodiment in accordancewith the present invention, it is to be understood that the same is notlimited thereto but is susceptible to numerous changes and modificationsas known to a person skilled in the art, and we therefore do not wish tobe limited to the details shown and described herein, but intend tocover all such changes and modifications as are obvious to one ofordinary skill in the art.

1-14. (Canceled)
 15. A demodulator comprising: an input port to which aninput signal containing an encoded information signal modulated onto acarrier frequency, and containing in-phase and quadrature phasecomponents, is applied; a frequency converter coupled to receive saidinput signal and a fixed frequency signal proximate said carrierfrequency and being operative to produce a frequency converted signalcontaining said encoded information signal; and a frequency errorcorrection loop coupled to process said frequency converted signal toproduce a corrected frequency converted signal, said frequency errorcorrection loop including a cordic rotator to which said frequencyconverted signal is coupled, said cordic rotator containing a quadrantadjustment section and a phase angle adjustment section, said correctedfrequency converted signal being output via an output port to downstreambaseband processing circuitry for recovering said information signal, aphase error detector coupled to the output of said cordic rotator andbeing operative to detect phase error in the output of said cordicrotator associated with a departure of said fixed frequency signal fromsaid carrier frequency, and a loop filter coupled to the output of saidphase detector and through which a phase error signal generated by saidphase error detector is coupled to said cordic rotator for controllingthe operation thereof; and wherein said output port from which saidcorrected frequency converted signal output by said cordic rotator isderived for application to said downstream baseband processing circuitryfor recovering said information signal is coupled to the output of saidcordic rotator of said frequency error correction loop.
 16. Thedemodulator according to claim 15, further including a digitizer whichis operative to digitize said frequency converted signal produced bysaid frequency converter, and wherein said frequency error correctionloop comprises a digital frequency error correction loop.
 17. Thedemodulator according to claim 16, wherein said cordic rotator isoperative to perform iterative adjustments of digitized in-phase andquadrature components of said frequency converted signal to reduce saidphase error detected by said phase error detector.
 18. A demodulatoraccording to claim 17, wherein said cordic rotator is operative toiteratively rotate digitized in-phase and quadrature components of saidfrequency converted signal in accordance with a phase angle vectorassociated with said phase error detected by said phase error detector.19. A demodulator according to claim 18, wherein said cordic rotator isoperative to iteratively adjust said digitized in-phase and quadraturecomponents of said frequency converted signal in association with aniterative modification of said phase angle vector in a phase angleiteration loop to which said phase error signal generated by said phaseerror detector is coupled, over a prescribed number of processingcycles.
 20. The demodulator according to claim 19, wherein said quadrantadjustment section of said cordic rotator is upstream of in-phase andquadrature-phase channel rotation iteration loops, and said phase angleadjustment section is upstream of a phase angle iteration loop, saidin-phase and quadrature-phase channel rotation iteration loops beingoperative to iteratively rotate respective quadrant adjusted values ofsaid digitized in-phase and quadrature components of said frequencyconverted signal to values associated with said phase angle iterationloop iteratively reducing an adjusted value of said phase angle vectorto a minimum value.
 21. A demodulator comprising: a frequency convertercoupled to receive an input signal containing an encoded informationsignal modulated onto a carrier frequency, and containing in-phase andquadrature phase components, and a fixed frequency signal proximate saidcarrier frequency, said frequency converter being operative to produce afrequency converted signal containing said encoded information signal;and a frequency error correction loop coupled to process said frequencyconverted signal to produce a corrected frequency converted signal,which is output via an output port to downstream baseband processingcircuitry for recovering said information signal, said frequency errorcorrection loop including a cordic rotator to which said frequencyconverted signal is coupled, said cordic rotator containing a quadrantadjustment section and a phase angle adjustment section, and having anoutput thereof coupled to said output port, a phase error detectorcoupled to the output of said cordic rotator and being operative todetect phase error in the output of said cordic rotator associated witha departure of said fixed frequency signal from said carrier frequency,and a loop filter coupled to the output of said phase detector andthrough which a phase error signal generated by said phase errordetector is coupled to said cordic rotator for controlling the operationthereof.
 22. The demodulator according to claim 21, further including adigitizer which is operative to digitize said frequency converted signalproduced by said frequency converter, and wherein said frequency errorcorrection loop comprises a digital frequency error correction loop. 23.The demodulator according to claim 22, wherein said cordic rotator isoperative to perform iterative adjustments of digitized in-phase andquadrature components of said frequency converted signal to reduce saidphase error detected by said phase error detector.
 24. A demodulatoraccording to claim 23, wherein said cordic rotator is operative toiteratively rotate digitized in-phase and quadrature components of saidfrequency converted signal in accordance with a phase angle vectorassociated with said phase error detected by said phase error detector.25. A demodulator according to claim 24, wherein said cordic rotator isoperative to iteratively adjust said digitized in-phase and quadraturecomponents of said frequency converted signal in association with aniterative modification of said phase angle vector in a phase angleiteration loop to which said phase error signal generated by said phaseerror detector is coupled, over a prescribed number of processingcycles.
 26. The demodulator according to claim 25, wherein said quadrantadjustment section of said cordic rotator is upstream of in-phase andquadrature-phase channel rotation iteration loops, and said phase angleadjustment section is upstream of a phase angle iteration loop, saidin-phase and quadrature-phase channel rotation iteration loops beingoperative to iteratively rotate respective quadrant adjusted values ofsaid digitized in-phase and quadrature components of said frequencyconverted signal to values associated with said phase angle iterationloop iteratively reducing an adjusted value of said phase angle vectorto a minimum value.